Fast Parallel PRBS Generator

A fast parallel PRBS generator can be implemented by using only N single latches. There are N parallel output that are N-decimated PRBS sequences from an original PRBS from an LFSR, shifted by n bits (n=0,1,...,N-1). The general-purpose schematic diagram is displayed below, followed by the specialized applet which may help a designer to complete the wiring depending on the customized need.

This scheme may possibly be applied to the parallel inputs of a muxing circuit. However, the constraint is that the number of stages (bits) in an LFSR has to be the same as the number of parallel branches.

Brief User's Guide

  • Fill in the text-field for the number of parallel branches, N
  • Click the "Get Coeffs" button to find a set of non-zero feedback coefficient for the given N value
  • Simply click the "Calculate" button to compute the appropriate wiring scheme

Reference

Paul H. Bardell, William H. McAnney, and Jacob Savir, "Built-In Test for VLSI: Pseudorandom Techniques", John Wiley & Sons, New York, 1987.

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